Recently, ROM has almost become requisite part in electronic products. FIG. 1 shows a circuit diagram of a conventional flat-cell ROM 100 and for simplification, only a memory bank of the ROM 100 is shown in FIG. 1. In the ROM 100, each memory bank comprises a memory array 102, a plurality of bit lines BL and virtual ground lines VG capable of being connected to the memory array 102, and select lines SL0 and SL1 to select the bit lines BL and virtual ground lines VG to be connected to the memory array 102, and the memory array 102 includes a plurality of transistors 104 serving as the memory cells, with the gates of the transistors 104 on a same row connected to one of word lines WL0˜WLN, such that data in each of the memory cells 104 may be read out by selecting the bit lines BL, virtual ground lines VG, and word lines WL0˜WLN. FIG. 2 shows a layout of the memory circuit shown in FIG. 1, with two memory banks Bank1 and Bank2 of the ROM 100 for illustration. In each of the memory banks Bank1 and Bank2, either a bit line BL or a virtual ground line VG is connected to a corresponding bit signal line 108 or a virtual ground line 110 through a respective contact 106.
To increase the memory density, there have been proposed various approaches to reduce the ROM area, for example in the flat-cell ROM disclosed in U.S. Pat. No. 5,117,389 to Yiu, less block select transistors is proposed to increase the memory density. As shown in FIG. 2, each memory bank of a conventional flat-cell ROM 100 is provided with two rows of the contacts 106 at the upper and lower sides of the memory bank, and each row of the contacts 106 occupies a chip area. Therefore, the flat-cell ROM 100 may have smaller ROM area, if the number of rows of the contacts 106 is reduced.